The present invention involves an electronic circuit for buffering binary state signals. More particularly, the invention prescribes a buffer circuit which effectively drives an output pad of a CMOS integrated circuit device while suppressing switching noise spikes on the supply voltage and ground lines of the device.
Integrated circuits have evolved to a level where the switching speeds of the logic field effect transistors are now so fast that the distributed inductances of the ground line as well as the power supply line produce voltage spikes of considerable magnitudes. As the device geometries and operating voltages decrease, logic circuits on such integrated circuits become even more susceptible to voltage spikes. Consequently, there has appeared a growing need for integrated circuit logic switching circuits which are capable of handling conventional current levels yet provide switching transitions which do not produce significant voltage spikes on either the ground or the power supply bus lines.
A number of techniques for controlling switching transients have been considered and likely implemented. One such approach is described in U.S. Pat. No. 4,129,792, wherein parallel driver transistors are enabled in fixed time delay succession to incrementally elevate the level of output current. The invention in U.S. Pat. No. 4,628,218 proposes the use of a parallel transistor, drawing current from a supplemental capacitor in lieu of the power supply line, to temporarily provide an elevated level of current to the output line. The successive enablement of parallel connected transistors is also central to the invention described in U.S. Pat. No. 4,638,187, here implemented in the context of cascaded CMOS inverter stages. U.S. Pat. No. 4,727,266, teaches that the rate of change of current in the output can be limited by undersizing the input stage drivers in relation to the capacitive load on the input node to the final inverter stage. Control of the output waveform to limit switching noise is also the subject of U.S. Pat. No. 4,731,553, in this case including the further refinement of having multiple power supplies for individual use by the successive driver stages. Using a current sink to time limit the supply voltage available at an input amplifier stage is the subject of U.S. Pat. No. 4,739,193. Sizing of the predriver stages to control output noise and match characteristic impedence is the subject of an article authored by Knight, Jr. et al., entitled "A Self-Terminating Low-Voltage Swing CMOS Output Driver" which appeared in the April 1988 issue of IEEE Journal of Solid-State Circuits. The paper entitled "Controlled Slow Rate Output Buffer" by Leung as appeared in the published proceedings of the IEEE 1988 Custom Integrated Circuits Conference, pages 5.51-5.54, describes a technique with features similar to the aforemention copending patent application. Also of potential interest is the switching noise suppression subject matter in U.S. Pat. Nos. 4,719,369 and 4,408,135.
The concept of body effect as related to the operating characteristics of a field effect transistors formed in a common substrate is relatively well known by those who routinely practice in the art. For instance, see the discussion which appears in Chapter 2.1.5 of the textbook entitled Principles of CMOS VLSI Design, authored by Weste et al., and published by Addison-Wesley with a copyright date of 1985.
TTL/CMOS interface circuits to control the characteristics of an output buffer are the subject of U.S. Pat. No. 4,437,024. Therein, parallel connected transistors of various widths are implemented to constrain terminal potentials within defined threshold and logic bands.
Though the various references bear upon the control of an output driver transistor or inverter pair, the variations, if nothing else, suggest that solutions to the problem of power supply and ground line spikes have yet to be eliminated in any routine or commonly practiced manner.